Dynamic logic circuits are typically preferred when fast circuits are required. A type of dynamic logic circuit is the domino logic circuit. Domino logic circuits typically utilize a clocking scheme to determine how to transfer from one phase to another. The term "clocking scheme" for a given gate denotes the assignment of the phases for each of the pins of the gate (inputs, clock and output). It is desirable to use only those clocking schemes that have the property of correcting any timing problems of the circuit by reducing the clock frequency. Such clocking schemes are typically referred to as robust clocking schemes.
There are typically two types of domino logic circuits. The first is a footed domino logic, in which each domino has an added N-type device whose function is to prevent short circuit in the device during a pre-charge phase. The other type of domino logic circuit does not require a foot device.
The footed domino logic typically utilizes two-phased clocking systems. In order to transfer from the first phase into the second phase, information can be passed along in various ways. One way is to have overlapping clock signals. However, it is typically very difficult to generate a set of overlapping clock signals. Another conventional method for transferring from the first phase into the second phase is to utilize a special gate which includes a latch as a storing element which allows transfer of information from the first phase to the second phase. However, this latch method typically suffers from poor performance. Chips utilizing this latch system are robust in that timing problems improve when the clock frequency is slowed down.
A problem with the footed domino logic circuit is that the foot device typically causes serious performance penalties.
The other type of domino logic circuit utilizes a clock with multiple phases. This type of domino logic is referred to as a delayed reset domino circuit. The delayed reset domino circuit does not require a foot device. This type of domino logic circuit can attain increased performance and allows switching from one phase to another without the need for latches. One problem associated with such a circuit utilizing multiphase clocks, is that when a multiple number of clock signals are utilized (at least three), the system needs to determine which combination of clock signals to use for each gate since the output of each domino gate depends on which clock signal it receives. For example, the system may need to determine which combination of twelve clock signals, of which there may be several hundred possibilities, are worth considering. Systematically eliminating each possibility can drastically reduce design productivity.
What is needed is a method for robust clocking schemes in a dynamic circuit which improves design productivity. The present invention addresses such a need.